******************* FILE 2 of 6 FILES **********************

(C) 31 JUL 88

Eric Gustafson,  N7CL
2018 S. Avenida Planeta
Tucson, AZ 85710



          DPLL  Derived Data Carrier Detect (DCD)
          For Filter Based and Single Chip Modems


                    CIRCUIT DESCRIPTION

The  circuit diagram is presented in Figure 1.   This is  an 
ASCII  representation of the schematic diagram.   While this 
isn't  really a proper "standard" diagram,  I believe it  is 
readable enough to be used to duplicate the circuit.  It has 
the  beneficial  characteristic that it requires no  CAD  or 
special  graphics software to be able to view  the  diagram.  
Thanks  to  Mykle Raymond,  N7JZT,  for making up  this  BBS 
forwardable ASCII schematic.

Figure 1 is contained in the last file in this series.

The  circuit consists of the state machine used in the TNC-2 
and some delay elements used to make the DCD decision.   The 
state  machine  is  formed from the 74HC374  and  the  27C64 
chips.   The 74HC14 is used as a pair of retriggerable delay 
elements and for signal inversion and buffering.

The 27C64 with the state machine code already burned into it 
can be obtained directly from TAPR.  If you wish to use this 
source for the part, please call Chris at (602)-323-1710 for 
price  and availability information.   This same code is  in 
the state machine ROM in any full TNC-2 clone which uses the 
2211  demodulator and Z80 SIO.   If sufficient  interest  is 
shown in this circuit,  maybe we can cajole TAPR into making 
circuit  boards  available.   This would vastly  reduce  the 
wiring task.

One  of the state machine signals (which was not used in the 
TNC-2) appears on pin 19 of the 27C64.   This signal is  the 
DPLL update pulse.   As long as the DPLL is correctly locked 
to  the  incoming data,  no pulses will appear on this  pin. 
When  the  DPLL is not locked to an  incoming  data  stream, 
there will be a continuous stream of pulses on this pin.

The  DPLL update signal is used in this circuit to retrigger 
the  first delay element so that it never times out so  long 
as DPLL update pulses are present.  If the pulses disappear, 
the delay element times out and generates the DCD signal.

The  output  from the first delay element keeps  the  second 
delay  element triggered so long as DCD is true.   When  DCD 
goes  false,  the  second  delay element  begins  a  timeout 
sequence  which keeps the DCD output true until the  timeout 
period expires.  This is the source of the DCD "hang time".

While  the circuit presented here is primarily intended  for 
1200 baud VHF FM operation,  it will also work well for  300 
baud HF packet work.   If this is your application, the time 
constants on the delay elements will have to be adjusted.  

The time constant of the "hang" generator (0.47 uF cap) will 
have  to  be  increased for 300 baud operation so  that  the 
total capacitance is 2.0 uF.

The  time  constant which is optimum for the  DCD  generator 
(the  0.1  uF  cap in fig.  1) will depend on  a  number  of 
factors  including the bandwidth of the radio used ahead  of 
the  modem.

You  should  pick  a  value  for  the  DCD  generator  delay 
capacitor such that the DCD circuit produces approximately a 
10 percent duty cycle of false DCD "ON" time.  The false DCD 
ON  time should be observed while monitoring receiver  noise 
on  a  channel which is ABSOLUTELY free of   ANY  narrowband 
signals which fall within the demodulator's passband.   This 
includes CW,  RTTY,  internal receiver birdies, AM carriers, 
computer  spurs,  packet data carriers,  etc.  A good way to 
assure  this  is  to let the receiver  monitor  the  S-9  or 
greater  output of a noise bridge with no antenna connected. 
Remember  to  have  the  filter  of  appropriate   bandwidth 
selected  and  centered  over the modem  passband.   for  HF 
packet,  this is a 500 Hz filter as is normally used for  CW 
and RTTY operation.

The  DCD generator delay capacitor will probably need to  be 
somewhere in the range of 2 to 4 times the 0.1 uF value used 
for 1200 baud.

Both  negative  true  and  positive  true  DCD  outputs  are 
provided so that you may use the polarity which is  required 
by your TNC.   Also,  JMP1 and JMP2 allow the DCD circuit to 
be configured to operate correctly from either a positive or  
negative  true CD output from whichever modem chip is  found 
in your TNC.

(continued in file #3)

EOF